Power aware minimization of complementary logic functions based on maximal HD


In this work, the authors consider the problem of logic minimization for a special class of Boolean networks, targeting low power implementation, using static CMOS logic. The authors start by framing a new binary minterm-value (BmV) matrix/binary max term-value (BMV) matrix for a binary 2-tuple, [mi (Mi), mj (Mj)], where HD (mi (Mi), mj (Mj)) is O(n), where… (More)


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