Power aware interface synthesis for bus-based SoC designs

@article{Liveris2004PowerAI,
  title={Power aware interface synthesis for bus-based SoC designs},
  author={Nikolaos D. Liveris and Prithviraj Banerjee},
  journal={Proceedings Design, Automation and Test in Europe Conference and Exhibition},
  year={2004},
  volume={2},
  pages={864-869 Vol.2}
}
In this paper we discuss the problem of interface synthesis for a system on a chip (SoC) such that the power consumption is minimized under some given latency constraints. Since the AMBA protocol has become one of the standard interfaces for SoC cores, we develop our interface synthesis methods around the AMBA protocol. We first provide an analysis of the parameters of the AMBA bus and the communication protocols and a bus power model thatwill be used by various transformations. Several latency… CONTINUE READING

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  • Experimental results are reported on two example benchmarks in that show that the heuristic is able to reduce power consumption on the wires by about 28% on the average from an initial design having a single layer bus architecture.
  • Experimental results are reported on two example benchmarks in that show that the heuristic is able to re­duce power consumption on the wires by about 28% on the average from an initial design having a single layer bus ar­chitecture.
  • Ex­perimental results are reported on two example benchmarks in Section 8 that show that the heuristic is able to reduce power consumption on the wires by about 28% on the av­erage from an initial design having a single layer bus archi­tecture.

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High-fidelity markovian power model for protocols

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A practical power model of AMBA system for high-level power analysis

  • 2009 International Symposium on VLSI Design, Automation and Test
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System-level power-performance trade-offs in bus matrix communication architecture synthesis

  • Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)
  • 2006
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