Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS

@article{Novo2009PowerawareEF,
  title={Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS},
  author={David Novo and Robert Fasthuber and Praveen Raghavan and Andr{\'e} Bourdoux and Min Li and Liesbet Van der Perre and Francky Catthoor},
  journal={2009 IEEE Workshop on Signal Processing Systems},
  year={2009},
  pages={151-156}
}
The raising cost of the latest technology nodes as well as the design cost associated has motivated an increasing push for flexible radio implementations. In this context, Sigma-Delta (ΣΔ) ADCs have emerged as a promising alternative to direct conversion. In this work a novel wireless receiver architecture based on an RF bandpass ΣΔ is considered. One of… CONTINUE READING