Power-aware NoCs through routing and topology reconfiguration

@article{Parikh2014PowerawareNT,
  title={Power-aware NoCs through routing and topology reconfiguration},
  author={Ritesh Parikh and Reetuparna Das and Valeria Bertacco},
  journal={2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)},
  year={2014},
  pages={1-6}
}
With the advent of multicore processors and system-on-chip designs, intra-chip communication demands have exacerbated, leading to a growing adoption of scalable networks-on-chip (NoCs) as the interconnect fabric. Today, conventional NoC designs may consume up to 30% of the entire chip's power budget, in large part due to leakage power. In this work, we address this issue by proposing Panthre: our solution deploys power-gating to provide long intervals of uninterrupted sleep to selected units… CONTINUE READING
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