Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systems

@article{Bhardwaj2014PowerAA,
  title={Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systems},
  author={Kartikeya Bhardwaj and Pravin S. Mane and J{\"o}rg Henkel},
  journal={Fifteenth International Symposium on Quality Electronic Design},
  year={2014},
  pages={263-269}
}
Today in sub-nanometer regime, chip/system designers add accuracy as a new constraint to optimize Latency-Power-Area (LPA) metrics. In this paper, we present a new power and area-efficient Approximate Wallace Tree Multiplier (AWTM) for error-tolerant applications. We propose a bit-width aware approximate multiplication algorithm for optimal design of our multiplier. We employ a carry-in prediction method to reduce the critical path. It is further augmented with hardware efficient precomputation… CONTINUE READING

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