Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations

Abstract

Ahsrrucr-3-D technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. One of the purposes of realizing 3-D integration b to reduce the interconnect complexity and delay of 2-D, which are widely avowed as the barriers to the continued performance gain in the future technology generations. ThereforeJn this paper, we present a stochastic 3-D interconnect model, study the impact of 3-D integration on circuit performance and power consumption. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters, and dramatically improve the circuit performance. With 3-D integration, circuits can be clocked at frequencies much higher (double, even triple) than with 2-D. However, we also show that the impacts of vertical wires on chip area and interconnect delay can be limiting factors on the vertical integration of device layers; and that 3-D integration offers limited relief of power consumption.

DOI: 10.1109/ISQED.2001.915230

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Cite this paper

@inproceedings{Zhang2001PowerTA, title={Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations}, author={Rongtian Zhang and Kaushik Roy and Cheng-Kok Koh and David B. Janes}, booktitle={ISQED}, year={2001} }