Power Supply Noise in Delay Testing

@article{Wang2006PowerSN,
  title={Power Supply Noise in Delay Testing},
  author={Jing Wang and D. M. H. Walker and Ananta K. Majhi and Bram Kruseman and Guido Gronthoud and Luis Elvira Villagra and Paul van de Wiel and Stefan Eichenberger},
  journal={2006 IEEE International Test Conference},
  year={2006},
  pages={1-10}
}
Excessive power supply noise can affect path delay and cause overkill during delay test. This paper presents low-cost noise models for fast power supply noise analysis and timing analysis considering noise impact. Our prior work only considered array-bond chips. This work proposes a noise analysis methodology that can be applied to wire-bond chips as well… CONTINUE READING

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