Latency-aware DVFS for efficient power state transitions on many-core architectures
The search for managing the increasing power consumption of today’s systems is still unbroken. The core idea of minimising power consumption while maximising the system’s performance has been approached in earlier work using frequency and voltage scaling. However, with the coming of multi-core systems new constraints are imposed on power management solutions which make the single-core solutions difficult to use. A new challenge brought by multi-core, multiprocessor systems are the different sleep states for cores and processors. In this work I present a new approach to power management for multi-core, multiprocessor systems. Using the different power levels of individual cores and whole processors of a multi-core, multiprocessor system, the system state is optimised in terms of power consumption and performance. To show the possible gain for a system’s power management I have implemented and evaluated a possible solution. To weight the cost of diminishing performance against a possible reduction in power consumption, a formal cost model of the system is created. The evaluation of the implemented solution shows a reduction in power consumption while keeping performance as high as possible.