• Corpus ID: 27443517

Power LDMOS with novel STI profile for improved Rsp, BVdss, and reliability

@article{Haynie2010PowerLW,
  title={Power LDMOS with novel STI profile for improved Rsp, BVdss, and reliability},
  author={S. Haynie and Ann Gabrys and Taeyeop Kwon and Paul Allard and Joe Strout and Andy Strachan},
  journal={2010 22nd International Symposium on Power Semiconductor Devices \& IC's (ISPSD)},
  year={2010},
  pages={241-244}
}
  • S. Haynie, A. Gabrys, A. Strachan
  • Published 6 June 2010
  • Engineering
  • 2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD)
The profile of shallow trench isolation (STI) is designed to improve LDMOS specific on-resistance (Rsp), BVDSS, safe operating area (SOA), and hot carrier lifetimes (HCL) in an integrated BiCMOS power technology. Silicon etch, liner oxidation and CMP processes are tuned to improve the tradeoffs in a power technology showing significant improvement to both p-channel and n-channel Rsp compared to devices fabricated with the STI profile inherited from the original submicron CMOS platform… 

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TLDR
The main purpose of this paper is to investigate device behaviour in the neighborhood of the SOA boundary and then use these results to predict theSOA, and show how a simplified two-terminal model of the drain region can be used to demonstrate the behaviour of the LDMOS as it approaches snap-back.
On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region
In this letter, on-resistance (<i>R</i> <sub>on</sub>) degradation induced by hot-carrier injection in n-type lateral DMOS transistors with shallow-trench isolation (STI) in the drift region is