Power Estimation and Optimization at the Logic Level

@inproceedings{Pedram2008PowerEA,
  title={Power Estimation and Optimization at the Logic Level},
  author={Massoud Pedram},
  year={2008}
}
This paper describes various approaches for power analysis and minimization at the logic level including amongst others pattern independent probabilistic and symbolic simulation techniques for power estimation and low power techniques for state assignment logic re structuring logic decomposition technology mapping and pin ordering 

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A Timing Analyzer for nMOS VLSI Circuits An incremental MOS switch level simulator

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