Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology


The 64 kB LI caches on the PA6T-1682M SoC CPU are composed of common data and tag structures fabricated in a 65 nm CMOS process and deliver a 1.5 cycle read latency with 32 GB/s bandwidth at 2 GHz. Several features optimize cache performance and power including power-down safe level shifters, streamlined dual-supply bitslices, fine-grain clock gating, and a… (More)
DOI: 10.1109/CICC.2007.4405834


10 Figures and Tables

Slides referencing similar topics