Power-Efficient Decision-Feedback Equalizers for Multi-Gb/s CMOS Serial Links

@article{Bulzacchelli2007PowerEfficientDE,
  title={Power-Efficient Decision-Feedback Equalizers for Multi-Gb/s CMOS Serial Links},
  author={J. F. Bulzacchelli and A. V. Rylyakov and D. J. Friedman},
  journal={2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium},
  year={2007},
  pages={507-510}
}
A decision-feedback equalizer (DFE) can compensate for severe signal distortion due to limited channel bandwidth, but its typical power consumption is too high for some applications. This paper describes three CMOS DFEs which embody different design techniques for improved power efficiency. The first one, with two taps, uses a soft decision technique to reduce the critical path delay of the first feedback tap, so that the analog summers can be operated at low currents. This DFE consumes 4.8 mW… CONTINUE READING

References

Publications referenced by this paper.
Showing 1-3 of 3 references

A 2-tap DFE employing current-integrating summers

  • S. Sidiropoulos, M. Horowitz
  • IEEE Int. Solid-State Circuits Conf: Dig. Tech…
  • 2007

capacitor voltages are sampled by a slicer and then reset

  • R. Payne
  • 2005

A 5 - mW 6 - Ck 1 / W . L Gb / s quarter - rate sampling receiver with a 2 - tap DFE using Ck . . soft decisions

  • J. Bulzacchelli M. Park, M. Beakes