Power Analysis Resistant SRAM


The power consumption of a standard CMOS SRAM during read/write operations is dependent on the address applied, the data accessed, and the type of access (read/write). The power analysis resistant SRAM structure presented in this work reduces the dependency of power consumption on data and address 10 times compared to standard SRAM at the expense of higher… (More)


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@article{Konur2006PowerAR, title={Power Analysis Resistant SRAM}, author={E. Konur and Y. Ozelci and Emel Arikan and U. Eksi}, journal={2006 World Automation Congress}, year={2006}, pages={1-6} }