Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks

@article{Homayoun2010PostsynthesisST,
  title={Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks},
  author={Houman Homayoun and Shahin Golshan and Elaheh Bozorgzadeh and Alexander V. Veidenbaum and Fadi J. Kurdahi},
  journal={2010 11th International Symposium on Quality Electronic Design (ISQED)},
  year={2010},
  pages={499-507}
}
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip power. In this paper, we propose to deploy sleep transistor insertion (STI) in the clock tree in order to reduce leakage power. We characterize the effect of sleep transistor sharing and… CONTINUE READING