Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks

@article{Akl2009PostSiliconC,
  title={Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks},
  author={Charbel J. Akl and Rafic A. Ayoubi and Magdy A. Bayoumi},
  journal={2009 10th International Symposium on Quality Electronic Design},
  year={2009},
  pages={794-798}
}
Proposed in this paper is a post-silicon technique and circuits that reduce random process-variation induced skew with simple leaf buffers modification of a buffered clock network. If a timing violation due to clock skew occurs during testing, the present technique offers a second chance via Post-Silicon Clock-Invert (PSCI), which decreases the probability… CONTINUE READING