Post-Placement Power Optimization With Multi-Bit Flip-Flops

@article{Lin2010PostPlacementPO,
  title={Post-Placement Power Optimization With Multi-Bit Flip-Flops},
  author={Mark Po-Hung Lin and Chih-Cheng Hsu and Yao-Tsung Chang},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2010},
  volume={30},
  pages={1870-1882}
}
Optimization for power is always one of the most important design objectives in modern nanometer IC design. Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network. However, all the previous works applied multi-bit flip-flops at earlier design stages, which could be very difficult to carry out the trade-off among power, timing, and other design objectives. This paper presents a novel power optimization method by… CONTINUE READING
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Using multi-bit register inference to save area and power: the good, the bad, and the ugly

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  • EE Times Asia, May 2001.
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