Polymorphic On-Chip Networks

  title={Polymorphic On-Chip Networks},
  author={Martha Mercaldi Kim and John D. Davis and Mark Oskin and Todd M. Austin},
  journal={2008 International Symposium on Computer Architecture},
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We begin this study with an area-performance analysis of the interconnect design space. We find that there is no single network design that yields optimal performance across a range of traffic patterns. This indicates that there is an opportunity to gain performance by customizing the interconnect to a particular application… CONTINUE READING
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