Plowing: Interactive Stretching and Compaction in Magic

@article{Scott1984PlowingIS,
  title={Plowing: Interactive Stretching and Compaction in Magic},
  author={Walter S. Scott and John K. Ousterhout},
  journal={21st Design Automation Conference Proceedings},
  year={1984},
  pages={166-172}
}
The Magic layout editor provides a new operation called plowing, for stretching and compacting Manhattan VLSI layouts. Plowing works directly on the mask-level representation of a layout, allowing portions of it to be rearranged while preserving connectivity and layout-rule correctness. The layout and connectivity rules are read from a file, so plowing is technology independent. Plowing is fast enough to be used interactively. This paper presents the plowing operation and the algorithm used to… 

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  • Computer Science
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  • 1985
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The historical background and the major developments in the field of compaction are reviewed, emphasizing subjective evaluations rather than objective descriptions.

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TLDR
The historical background and the major developments in the field of compaction are reviewed, emphasizing subjective evaluations rather than objective descriptions.

A Faster One-Dimensional Topological Compaction Algorithm with Jog Insertion

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By combining both geometric and graph-theoretic approaches, this work presents a faster and simpler algorithm to improve over previous results in the problem of one-dimensional topological compaction with jog insertions.

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References

SHOWING 1-10 OF 11 REFERENCES

Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools

  • J. Ousterhout
  • Computer Science
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 1984
TLDR
The algorithms are presented under a simplified model of VLSI circuits, and the storage requirements of the structure are discussed.

Magic: A VLSI Layout System

TLDR
The Magic layout system incorporates expertise about design rules and connectivity directly into the layout system in order to implement powerful new operations, including: a continuous design-rule checker that operates in background to maintain an up-to-date picture of violations.

Virtual Grid Symbolic Layout

  • N. Weste
  • Computer Science
    18th Design Automation Conference
  • 1981
TLDR
A new compaction strategy which uses the concept of a virtual grid is presented, both simple and fast, an attribute which allows the designer to conveniently interact with the algorithm to optimize a layout.

STICKS - A graphical compiler for high level LSl design

TLDR
STICKS is a computer aided design system which frees the designer from the tedious aspects of IC design and allows him to concentrate on the more creative and necessarily human side of the design process.

A Vertically Integrated VLSI Design Environment

A VLSI design system called VIVID is the heart of a newly developed, vertically integrated design environment. This environment provides support for all phases of design from high-level system

Magic's Incremental Design-Rule Checker

TLDR
The basic rule checker, which operates on edges in the layout, and the techniques used to perform incremental checking on hierarchical designs are described.

A Symbolic Design System for Integrated Circuits

TLDR
This paper describes a symbolic design system, its associated data manager, its color graphics viewport manager, and its application to a variety of design methods.

Paper

Paper is the primary medium for the formal publication of information, although it represents only 0.01% of new information recorded in all media. Information is recorded on paper in three distinct

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