Plenary II: Energy-efficient and ultra low voltage design pf sub-14nm SoCs and microprocessors: Challenges and opportunities


This talk presents some of the prominent barriers to designing energy-efficient circuits in the sub-14nm CMOS technology regime and outlines new paradigm shifts necessary in next-generation multi-core microprocessors and systems-on-chip. Emerging trends and key challenges in sub-14nm design are outlined, including (i) device and on-chip interconnect… (More)


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