Plasma etch and dielectric deposition processes for TSV Reveal

@article{Buchanan2011PlasmaEA,
  title={Plasma etch and dielectric deposition processes for TSV Reveal},
  author={Keith Buchanan and Dave Thomas and Hefin Griffiths and Kathrine Crook and Daniel Archard and Mark Carruthers and Masahiko Tanaka},
  journal={2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International},
  year={2011},
  pages={1-2}
}
Through-Silicon Vias [TSV] offer improved system performance by reducing interconnect length to increase device speeds, and by using stacking to reduce package form-factors and enabling heterogeneous device integration. Via Reveal' [VR] - a sequence of wafer back side process steps - is key to the successful implementation of TSV. After via formation, typically using a via-middle approach, finished CMOS wafers or interposers are temporarily bonded, face-down, to glass carriers. The TSV are then… CONTINUE READING
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