Placement of clock gates in time-of-flight optoelectronic circuits.


Time-of-flight synchronized optoelectronic circuits capitalize on the highly controllable delays of optical waveguides. Circuits have no latches; synchronization is achieved by adjustment of the lengths of waveguides that connect circuit elements. Clock gating and pulse stretching are used to restore timing and power. A functional circuit requires that every feedback loop contain at least one clock gate to prevent cumulative timing drift and power loss. A designer specifies an ideal circuit, which contains no or very few clock gates. To make the circuit functional, we must identify locations in which to place clock gates. Because clock gates are expensive, add area, and increase delay, a minimal set of locations is desired. We cast this problem in graph-theoretical form as the minimum feedback edge set problem and solve it by using an adaptation of an algorithm proposed in 1966 [IEEE Trans. Circuit Theory CT-13, 399 (1966)]. We discuss a computer-aided-design implementation of the algorithm that reduces computational complexity and demonstrate it on a set of circuits.

DOI: 10.1364/AO.34.008125

Cite this paper

@article{Feehrer1995PlacementOC, title={Placement of clock gates in time-of-flight optoelectronic circuits.}, author={John R. Feehrer and Harry F. Jordan}, journal={Applied optics}, year={1995}, volume={34 35}, pages={8125-36} }