Advances in the chip fabrication technology have begun to make manufacturing 3D chips a reality. For 3D designs to achieve their full potential, it is imperative to develop effective physical design strategies that handle the complexities and new objectives specific to 3D designs. We present two frameworks of placement and routing techniques, for 3D FPGA and for 3D standard cell based designs, respectively. Our method addresses wire length, delay and area minimization, as well as thermal optimization during placement and routing phases. These two flows have been used to obtain optimized layouts for benchmarks with upto 8000 FPGA blocks and tens of thousands of standard cells, respectively.