Placement and Routing for Three-Dimensional FPGAs

  title={Placement and Routing for Three-Dimensional FPGAs},
  author={Michael J. Alexander and James P. Cohoon and John Karro and Edward L. Peters and A Gabriel and RobinsDepartment},
We explore physical layout for a three-dimensional (3D) FPGA architecture. For placement, we introduce a top-down partitioning technique based on rectilinear Steiner trees; we then employ a one-step router to produce the nal layout. Experimental results indicate that our approach produces eeective 3D layouts, using considerably shorter average interconnect distance than is achievable with conventional 2D FPGA's of comparable size. 
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