Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits

@article{Chen2010PlacementOF,
  title={Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits},
  author={Jwu-E Chen and Pei-Wen Luo and Chin-Long Wey},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2010},
  volume={29},
  pages={313-318}
}
  • Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey
  • Published in
    IEEE Transactions on Computer…
    2010
  • Computer Science
  • Capacitor mismatch can generally result from two sources of error: random mismatch and systematic mismatch. Random mismatch is caused by process variation, while systematic mismatch is mainly due to an asymmetrical layout and processing gradients. A common centroid structure may be used to reduce systematic mismatch errors, but not random mismatch errors. Based on the spatial correlation model, this paper formulates the placement optimization problem of analog circuits using switched-capacitor… CONTINUE READING

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