Corpus ID: 163160780

Pipelined High Speed Double Precision Floating Point Multiplier Using Dadda Algorithm Based on FPGA

@inproceedings{Kumar2015PipelinedHS,
  title={Pipelined High Speed Double Precision Floating Point Multiplier Using Dadda Algorithm Based on FPGA},
  author={J. Kumar and G. R. Mohan and Sudershanraju},
  year={2015}
}
Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented in HDL. This paper presents a high speed binary double precession floating point multiplier based on Dadda Algorithm. To improve speed multiplication of mantissa is done using Dadda multiplier replacing Carry Save Multiplier. In… Expand

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