Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes

@article{Bhatt2006PipelinedBD,
  title={Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes},
  author={Tejas M. Bhatt and Vishwas Sundaramurthy and Victor Stolpman and Dennis McCain},
  journal={2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings},
  year={2006},
  volume={4},
  pages={IV-IV}
}
We present a pipelined block-serial decoder architecture for structured LDPC codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder by about 2x-3x and has negligible performance loss when implemented with clever layer scheduling. We also present a low-complexity check-node architecture suitable for block-serial processing and… CONTINUE READING
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Irregular Structured LDPC Codes”, IEEE 802.16 Broadband Wireless Working Group, contribution IEEE C802.16e- 04/264

  • V. Stolpman et. al
  • 2004
Highly Influential
3 Excerpts

Analysis of Scaling Soft Information On Low-Density Parity-Check Code

  • J. Heo
  • IEEE Electron. Lett., vol. 39,
  • 2003
1 Excerpt

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