• Corpus ID: 43341514

Pipelined Asynchronous Circuits

  title={Pipelined Asynchronous Circuits},
  author={Andrew Lines},
This thesis presents a design style for implementing communicating sequential processes (CSP) as quasi delay insensitive asynchronous circuits, based on the compilation method of [1]. Although hand compilation can always yield optimal circuits to a good designer, a restricted approach is suggested which can easily implement circuits with some slack between inputs and outputs. These circuits are fast and versatile building blocks for highly pipelined designs. The first chapter presents the… 

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