Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources

@inproceedings{Dong2013PipelineTA,
  title={Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources},
  author={Yazhuo Dong and Wu Zhan and Xiqing Ye},
  booktitle={ACM Great Lakes Symposium on VLSI},
  year={2013}
}
There are large numbers of high-level algorithms consisting of multiple loop nests in image compression, pattern recognition and digital signal processing. FPGA provides a convenient and flexible solution to speed up these loop-intensive algorithms. However, FPGA reconfiguration which needs a long time is inevitable when switching between the loop nests… CONTINUE READING