Physical verification flow for hierarchical analog ic design constraints

Abstract

Design constraints describe the intent of IC designers when developing electronic circuits. Constraints from, e.g., electrical and thermal domains are transformed into corresponding physical constraints for layout design. Physical constraints can also be derived from circuit patterns or extracted layout netlists. The constraint verification is of utmost… (More)
DOI: 10.1109/ASPDAC.2015.7059047

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Cite this paper

@article{Bexten2015PhysicalVF, title={Physical verification flow for hierarchical analog ic design constraints}, author={Volker Meyer zu Bexten and Markus Tristl and G{\"o}ran Jerke and Hartmut Marquardt and Dina Medhat}, journal={The 20th Asia and South Pacific Design Automation Conference}, year={2015}, pages={447-453} }