Physical register inlining

  title={Physical register inlining},
  author={Mikko H. Lipasti and Brian R. Mestan and Erika Gunadi},
  journal={Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.},
Physical register access time increases the delaybetween scheduling and execution in modern out-of-orderprocessors. As the number of physical registers increases,this delay grows, forcing designers to employ register fileswith multicycle access. This paper advocates more efficientutilization of a fewer number of physical registers in orderto reduce the access time of the physical register file. Registervalues with few significant bits are stored in the renamemap using physical register inlining… CONTINUE READING
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