Physical placement driven by sequential timing analysis

  title={Physical placement driven by sequential timing analysis},
  author={Aaron P. Hurst and Philip Chong and Andreas Kuehlmann},
  journal={IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.},
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the potential of re-balancing path delays through post-placement applications of clock skew scheduling and in-place retiming cannot be fully realized. In this paper we describe a new placement algorithm that is based on a tight integration of sequential timing analysis in the inner loop of an analytic solver. Instead of… CONTINUE READING
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Publications referenced by this paper.
Showing 1-10 of 20 references

Physical Planning with Retiming

ICCAD • 2000
View 9 Excerpts
Highly Influenced

RITUAL: A performance-driven placement algorithm

A. Srinivasan, K. Chaudhary, E. S. Kuh
IEEE Transactions on Circuits and Systems, vol. 37, pp. 825–839, November 1992. • 1992
View 6 Excerpts
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Synthesis of clock tree topologies to implement nonzero clock skew schedule

I. S. Kourtev, E. G. Friedman
IEE Proceedings on Circuits, Devices, Systems, vol. 146, pp. 321–326, December 1999. • 1999
View 1 Excerpt

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