Physical design of a fourth-generation POWER GHz microprocessor

@article{Anderson2001PhysicalDO,
  title={Physical design of a fourth-generation POWER GHz microprocessor},
  author={C. J. Anderson and John G. Petrovick and J. Keaty and J. Warnock and Gilles Nussbaum and J. M. Tendier and C. Carter and Sam G. Chu and Joachim G. Clabes and Jack DiLullo and Phillippa Dudley and Patricia Harvey and Byron Krauter and Jim LeBlanc and Pong-Fei Lu and B. D. McCredie and Georg Plum and P. J. Restle and Steve Runyon and Marciele M{\'a}rcia Scheuermann and Stephan Schmidt and J. Wagoner and Reinhold Weiss and Steve Weitzel and Bojan J Zoric},
  journal={2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)},
  year={2001},
  pages={232-233}
}
The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu/m SOI technology, with 7 layers of Cu interconnect, and functions in systems at 1.1 GHz, and dissipates 115 W at 1.5 V. 

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