Pin accessibility-driven cell layout redesign and placement optimization
Producing working chips in current (32nm) and forthcoming CMOS technologies feels a lot like trying to create an intricate oil painting using a broom! After all, we are using light with a wavelength of 193nm to create shapes less than a tenth of a wavelength in dimension. But this pheneomena is well known to all who work in the area of VLSI, and much has been made of the tremendous gains our industry has made over the years. These innovations and gains will need to continue for a few more years, at least, until the replacement for Silicon is found. As we have continued technology scaling, the physical design rules that constrain what the layout of a circuit look like have changed. In earlier technologies, design rules were driven primarily by equipment and material limitations, as well as particulate contamination (defects). In today's technologies, the design rules have become much more complex because they are now being increasingly driven by lithographic constraints. One important new phenomena has been the increase in design rules that enforce various forms of regularity on the design. Restricted polysilicon orientation, width and pitch being one common example. From this perspective, one can imagine a scenario where increasing layout restrictions are applied in order to allow further scaling. Since different layers have different resolution requirements, with the top-most metal layers (so-called <i>fat</i> metal) having the least challenging lithography, such layout restrictions will likely be applied bottom up. Thus the bottom-most metal layers, which have the tightest design rules, get impacted by regularity first, followed by the intermediate layers, and so on. If we examine current layout practice at the 32nm node, we observe that the polysilicon layer is already quite regular. The <i>hard</i> lithography problems, however, have migrated to the first metal layer -commonly referred to as M1. The M1 layer typically has similar dimensions to the polysilicon layer, so it is understandable that it would present significant lithography challenges. Furthermore, creating dense layouts of complex circuit topologies like latches and multiplexors cannot be done without introducing a certain amount of topological complexity in within-cell routing. Herein lies the first challenge in moving to the 22nm node and beyond: balancing the desire for density with that of image fidelity. How can physical design help with this problem? It strikes the author that much attention is paid to numerous global aspects of physical chip design, i.e. placement, global routing, congestion management and so on. But in the end, the assumption is that the individual leaf cells are fixed, opaque (except for pin locations perhaps) and -- most disturbingly --uninteresting. While some of this information hiding is necessary to manage the complexity of the design process, one cannot help thinking of ways in which some effective cross-optimization might happen.
Unfortunately, ACM prohibits us from displaying non-influential references for this paper.
To see the full reference list, please visit http://dl.acm.org/citation.cfm?id=1735029.