Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability

  title={Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability},
  author={J. Galiay and Yves Crouzet and M. Vergniault},
  journal={IEEE Transactions on Computers},
At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to check response times under nominal operating conditions, and 3) functional tests to check its logical behavior. 
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Optimal detection of bridging faults and stuckatfaults , in two - level logic

M. G. Karpovsky, E. S. Moskalev, S. Y. H. Su, P. R. Menon
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Definition and design of easily testable or selftesting LSI circuits " ( in French ) , Contract Rep

J. Galiay Y. Crouzet, C. Landrault, P. Rousseau, M. Vergniault

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