Phase-locked loops

@article{Gupta1975PhaselockedL,
  title={Phase-locked loops},
  author={S.C. Gupta},
  journal={Proceedings of the IEEE},
  year={1975},
  volume={63},
  pages={291-306}
}
  • S.C. Gupta
  • Published 1 February 1975
  • Engineering
  • Proceedings of the IEEE
An attempt to systematically outline the work done in the area of phase-locked loops which are now used in modern communication system design is presented. The analog phase-locked loops are well documented in several books but discrete, analog-digital, and digital. phase-locked loop work is scattered. Apart from discussing the various analysis, design, and application aspects of phase-locked loops, a number of references are given in the bibliography. 
Phase-locked loops: a control centric tutorial
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  • Computer Science
  • Proceedings of the 2002 American Control Conference (IEEE Cat. No.CH37301)
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Presents a tutorial on phase-locked loops from a control systems perspective. It starts with an introduction of the loop as a feedback control problem, with both the similarities and differences toExpand
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A new type of floating phase locked loops for DSP is designed and for the floating phase lock loops new stability conditions are obtained. Expand
THE AUTOMATED SOFTWARE PHASE-LOCKED LOOP AND THE EXPLORATION OF AN ADAPTIVE ALGORITHM FOR THE ADJUSTMENT OF PLL PARAMETERS
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This document describes the development of a software phase-locked loop and an algorithm to automate the selection of PLL parameters based upon measurements of the input signal and an adaptive algorithm for the adjustment of P LL parameters in real-time is investigated. Expand
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A systematic survey of the theoretical/experimental work accomplished in the area of digital phase-locked loops (DPLL's) during the period of 1960 to 1980, thereby offering speedy access to the techniques and hardware developments which have been presented in a scattered literature. Expand
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Methods to accurately measure phase-locked loop lock time in multisite production environment and inverse FFT was used to measure the PLLLock time in a case when PLL frequency error exists. Expand
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  • Larry Zhang
  • Engineering, Computer Science
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Methods to accurately measure a phase-locked loop lock time in a multisite production environment and fast Fourier transform techniques are used to measure the lock time for output frequency error exists. Expand
The Early History of Phase-Locked Loops
A browse through the phase-locked loop literature of the past is humbling. Although we often consider phase-locked loops as relatively new structures, historical literature dates the concept as earlyExpand
Acquisition performance of a digital phase locked loop with a four-quadrant arctan phase detector
  • S. Kandeepan, S. Reisenfeld
  • Physics
  • Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, 2004. ISPACS 2004.
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The acquisition performance of a digital phase locked loop (DPLL) with a four-quadrant arctan based phase detector (PD) is discussed. In the noiseless case, unlike the traditional sine function basedExpand
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References

SHOWING 1-10 OF 141 REFERENCES
On Optimum Digital Phase-Locked Loops
TLDR
The design procedure of optimum digital filters for analog-digital phase-locked loops is given and it is shown that the optimum digitalanalog phase- Locked loop is not the discrete version of the optimum continuous phase-lock loop. Expand
Gated Phase-Locked Loop Study
  • B. Eisenberg
  • Engineering
  • IEEE Transactions on Aerospace and Electronic Systems
  • 1971
The objectives of this paper are threefold. The first is to obtain a sampled data model of a gated phase-locked loop. Data from measurements made on an actual loop constructed in the laboratory areExpand
An all digital phase locked loop for FM demodulation.
A phase-locked loop designed with all-digital circuitry which avoids certain problems, and a digital voltage controlled oscillator algorithm are described. The system operates synchronously andExpand
Digital Phase Control Techniques
TLDR
It is concluded that over most of the range of operation the behavior of the digital phase-locked loop is nearly identical to the corresponding analog phase- Locked loop, but that in addition, certain possible advantages may occur as a result of the digitization. Expand
A Class of All Digital Phase Locked Loops: Modeling and Analysis
TLDR
An all digital phase locked loop which tracks the phase of the incoming signal once per carrier cycle is proposed and the lock range for the general model is derived. Expand
Range Extension of a Phase-Locked Loop
TLDR
An approximate method of estimating the locking range and the locking time of the HLL in the noisy environment has been presented and the experimental results in partial support of the conclusions of the analysis are given. Expand
Response of an All Digital Phase-Locked Loop
TLDR
It is found, using a computer simulation of a noise spike, and verified experimentally, that of these configurations the second-order system is optimum from the standpoint of threshold extension. Expand
On the Equivalence in Performance of Several Phase-Locked Loop Configurations
TLDR
If the loop parameters are defined appropriately, then the dynamic noise performance of the loop is identically equivalent to that of a standard phase-locked loop or a double-superheterodyne tracking loop using a noise-free external reference generator. Expand
A Model Distribution for the Phase Error in Second-Order Phase-Locked Loops
TLDR
Compared to the actual measurements of the second-order loop performance, it is shown that the model distribution provides excellent agreement over the useful range of most phase-locked receivers. Expand
Phase-Locked Loop Pull-In Range
In this paper the derivation of a general equation for the pull-in range of a phase-locked loop is outlined. The equation is applied to a typical third-order loop, and algebraic results are derivedExpand
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