High-speed DRAM interface standards create significant design challenges, especially in the multi-GHz realm. As unit intervals shrink, read latency control becomes one of the more difficult problems to solve. High data rate SDRAM specifications require the use of DLL circuits to generate read clocks, which, in turn, creates an indeterminate and time-varying phase boundary between the command/address (C/A) clock and the read data clock domains. This clock domain crossing must be managed to guarantee that read latency is determinate under all conditions. A similar latency problem exists for write data because of the arbitrary phase relationship between write data capture circuits and the command decoder circuit. In this paper, circuit techniques are described to manage both read and write latency in a high data rate GDDR3/GDDR4 capable device. These techniques are incorporated in a 512Mb SDRAM operating up to 2Gb/s/pin in GDDR3 mode and up to 2.5Gb/s/pin in GDDR4 mode.