Corpus ID: 2300979

Phase Noise Reduction Approach in PLL based Frequency Synthesizer for IEEE1394 PHY Applications

@inproceedings{Zhu2020PhaseNR,
  title={Phase Noise Reduction Approach in PLL based Frequency Synthesizer for IEEE1394 PHY Applications},
  author={Kehan Zhu and V. Saxena and X. Wu and J. Yue and Hairun Qi and Q. Li and A. Hajimiri and S. Limotyrakis and T. H. Lee and Jia Lin and J. Ma and K. Yeo and X. Gao and E. Klumperink and M. Bohsali and W. Rhee and M. Tamaddon and Milad Ataei and A. Nabavi and T. Weigandt and B. Kim},
  year={2020}
}
Technology advances have made gigabit signal a viable and attractive. A method to design IEEE 1394 based 1GHz Phase Locked Loop (PLL) system as frequency synthesizer with Low Phase Noise is proposed. A complementary LC oscillator is used to generate the 1GHz oscillation frequency and is divided into lower frequency clock by the feedback frequency divider. The architecture is type II third order charge pump Phase Locked Loop. In order to suppress spurs and reduce ripples on control voltage a… Expand
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