Corpus ID: 17723346

Phase Frequency Detector and Charge Pump For DPLL Using 0.18µm CMOS Technology

@inproceedings{Patel2013PhaseFD,
  title={Phase Frequency Detector and Charge Pump For DPLL Using 0.18µm CMOS Technology},
  author={Kashyap Patel and Nilesh D. Patel},
  year={2013}
}
  • Kashyap Patel, Nilesh D. Patel
  • Published 2013
  • Engineering
    • This paper presents a Low power phase frequency detector with charge pump for low power phase lock loop. The phase frequency detector with dead zone compensation has been proposed. The paper contains the detailed circuit diagram of PFD and charge pump with 1.8v power supply and 500MHz input frequency. The design has been realized using 0.18um CMOS technology. 
    14 Citations
    Highly Influential Citations
    1
    Background Citations
    9
    Methods Citations
    1
    14 Citations
    Citation Type

    Citation Type

    Charge Pump, Loop Filter and VCO for Phase Lock Loop Using 0.18µm CMOS Technology
    • 9
    • PDF
    TECHNOLOGY Low Power and Low Dead Zone Phase Frequency Detector in PLL
    Design of Phase Frequency Detector (PFD),Charge Pump (CP) and Programmable Frequency Divider for PLL in 0.18um CMOS Technology
    • 4
    An Ultra Low Power Fast Locking CMOS Phase Locked Loop for Wireless Communication
    • 1
    Performance Analysis of Low Power CSVCO for PLL Architecture
    • S. Saw, V. Nath
    • Computer Science
    • 2015 Second International Conference on Advances in Computing and Communication Engineering
    • 2015
    • 1
    • Highly Influenced
    A low power low noise current starved CMOS VCO for PLL
    • S. Saw, V. Nath
    • Computer Science
    • International Conference on Computing, Communication & Automation
    • 2015
    • 3
    Implementation and analysis of fast locking 5GHz phase locked loop
    • 2
    Charge Pump and Loop Filter for Low Power PLL Using 130nm CMOS Technology
    • 1
    EDR-BLE transmitter using power gating technique in 45 nm technology
    • P. Pream, S. Tamilselvan
    • Computer Science
    • 2017 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS)
    • 2017
    Phase Locked Loop Design and Implementation using Current Starved Voltage Controlled Oscillator
    • 1

    References

    SHOWING 1-10 OF 13 REFERENCES
    High Speed PFD with Charge Pump and Loop Filter for Low Jitter and Low Power PLL
    • 13
    • PDF
    A compact, low-power low-jitter digital PLL
    • A. Fahim
    • Engineering
    • ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705)
    • 2003
    • 46
    • PDF
    The design of a low-power low-noise phase lock loop
    • 17
    • PDF
    Low Jitter Phase-Locked Loop
    • 1
    • PDF
    CMOS Circuit Design, Layout, and Simulation
    • 2,715
    • PDF
    CMOS: Circuit Design, Layout, and Simulation (IEEE Press Series on Microelectronic Systems)
    • 49
    0.18μm Phase / Frequency Detector and Charge Pump Design for Digital Video Broadcasting for Handheld " s PLL Systems
    • 0.18μm Phase / Frequency Detector and Charge Pump Design for Digital Video Broadcasting for Handheld " s PLL Systems
    • 2007
    0.18μm Phase / Frequency Detector and Charge Pump Design for Digital Video Broadcasting for Handheld"s PLL Systems
    • 2007
    0.18μm phase/frequency detector and charge pump design for digital video broadcasting for handheld’s phase-locked-loop systems
    • 15
    Phase / Frequency Detector and Charge Pump Design for Digital Video Broadcasting for Handheld‟s
    • PLL Systems”,
    • 2007