Petri net modeling of gate and interconnect delays for power estimation

@inproceedings{Murugavel2002PetriNM,
  title={Petri net modeling of gate and interconnect delays for power estimation},
  author={Ashok K. Murugavel and N. Ranganathan},
  booktitle={DAC},
  year={2002}
}
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit is converted into a HCHPN and simulated as a Petri net to get the switching activity estimate and thus the power values. The method is accurate and is significantly faster than other simulative methods. The HCHPN yields an average error of 4.9% with respect to Hspice for the ISCAS '85 benchmark circuits. The per-pattern… CONTINUE READING

References

Publications referenced by this paper.
Showing 1-2 of 2 references

Najm.High-level power estimationwith interconnecteffects.In Proc.of theIntl

N.K.M. BuyuksahinandF
Symp.on LowPowerElectronicDevices, • 2000
View 4 Excerpts
Highly Influenced

KahngandS.Muddu.Gateloaddelaycomputation usinganalyticalmodels.In Proc.of Asia-PacificConference onCircuitsandSystems

A B.
1996
View 5 Excerpts
Highly Influenced

Similar Papers

Loading similar papers…