Performances of the AES design in 0.18μm CMOS technology

@article{Mestiri2012PerformancesOT,
  title={Performances of the AES design in 0.18μm CMOS technology},
  author={Hassen Mestiri and Mohsen Machhout and Rached Tourki},
  journal={7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era},
  year={2012},
  pages={1-6}
}
The Advanced Encryption Standard (AES) has been studied by designers with the goal to improve its performances in terms of area, power consumption and frequency. In this paper, we present the implementation details of the AES encryption 128-bit, the MixColumns transformation and the SubBytes transformation. The latter can be implemented using a multi-stage PPRM architecture and composite field arithmetic in GF(((22)2)2). In addition, the MixColumns transformation is used in two architectures… CONTINUE READING