• Corpus ID: 212595476

Performance of Prioritized i-SLIP Algorithm with Multiple Input Queued Switch

  title={Performance of Prioritized i-SLIP Algorithm with Multiple Input Queued Switch},
  author={S. N. Kore and Dr. P. J. Kulkarni},
Input Queued Switch has throughput limitation of 58%.Hence concept of Virtual Output Queue is evolved. Selection of ‘N’ cells out of N is difficult task. Prof.Nick Mckeown from Stanford University had suggested i-slip algorithm to provide throughput of 100%. Multiple Input Queued Switch is generalized case of Input Queued Switch, where M indicates number of queues/port. When M=N, its VOQ. When M=4, still 90% throughput can be obtained. Our attempt is to analyze the performance of MIQ with i… 


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  • IEEEACM trans
  • 1999
Input versus Output Queuing on a Space Division Switch
  • IEEE Transaction on Communications. Vol.35,
  • 1987
Survey of switch architectures
  • Elsevier Computer network and ISDN systems
  • 1995
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