• Corpus ID: 212595476

Performance of Prioritized i-SLIP Algorithm with Multiple Input Queued Switch

@inproceedings{Kore2015PerformanceOP,
  title={Performance of Prioritized i-SLIP Algorithm with Multiple Input Queued Switch},
  author={S. N. Kore and Dr. P. J. Kulkarni},
  year={2015}
}
Input Queued Switch has throughput limitation of 58%.Hence concept of Virtual Output Queue is evolved. Selection of ‘N’ cells out of N is difficult task. Prof.Nick Mckeown from Stanford University had suggested i-slip algorithm to provide throughput of 100%. Multiple Input Queued Switch is generalized case of Input Queued Switch, where M indicates number of queues/port. When M=N, its VOQ. When M=4, still 90% throughput can be obtained. Our attempt is to analyze the performance of MIQ with i… 

References

SHOWING 1-9 OF 9 REFERENCES
A Performance Evaluation of Multiple Input Queued (MIQ) Switch with Iterative Weighted Slip Algorithm
TLDR
This attempt is to use MIQ architecture and evaluate delay, throughput performance with i-slip algorithm for scheduling and used Bernoulli’s and Bursty (ON-OFF) traffic models.
Queueing in high-performance packet switching
TLDR
Output queuing and completely shared buffering both achieve the optimal throughput-delay performance for any packet switch, however, compared to output queuing, completely sharedbuffering requires less buffer memory at the expense of an increase in switch fabric size.
The iSLIP scheduling algorithm for input-queued switches
TLDR
This paper presents a scheduling algorithm called iSLIP, an iterative, round-robin algorithm that can achieve 100% throughput for uniform traffic, yet is simple to implement in hardware, and describes the implementation complexity of the algorithm.
Fast and Noniterative Scheduling in Input-Queued Switches
TLDR
A new scheduling algorithm is proposed that finds a maximum matching of a modified I/O mapping graph in a single iteration (hence noniterative) and provides full throughput and incurs very low delay; it is fair and of low complexity; and it outperforms traditional iterative schedulers.
Design and Implementation of a Fast VOQ Scheduler for a Switch Fabric
TLDR
The way of designing and implementing of Prioritized iSLIP algorithm on FPGA, an iterative algorithm that provides high efficiency for best-effort traffic, is described.
i-slip Scheduling Algorithm for input- Queued Switches
  • IEEEACM trans
  • 1999
Input versus Output Queuing on a Space Division Switch
  • IEEE Transaction on Communications. Vol.35,
  • 1987
Survey of switch architectures
  • Elsevier Computer network and ISDN systems
  • 1995
The i-slip Scheduling Algorithm for input-Queued Switches