Performance evaluation of Butterfly on-Chip Network for MPSoCs


By Technology improvement, tens or hundreds of IP cores, operating complex functions with different frequencies, are mapped on-chip. This results in heterogeneous multiprocessor system-on-chip (MPSoC). The most MPSoC design challenges are due to infrastructure interconnect. Network-on-chip (NoC) with multiple constraints to be satisfied is a promising… (More)

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@article{Arjomand2008PerformanceEO, title={Performance evaluation of Butterfly on-Chip Network for MPSoCs}, author={Mehdi Arjomand and Hamid Sarbazi-Azad}, journal={2008 International SoC Design Conference}, year={2008}, volume={01}, pages={I-296-I-299} }