Performance evaluation for optical network-on-chip interconnect architectures

Abstract

A large number of IP cores will be included in the future systems-on-chip (SoC). Traditional bus-based architectures are no longer suitable for modern chip design, since it is difficult to expand, consumes much power and takes much area. Network-on-chip (NoC), which employs networks to replace buses as a scalable global communication platform, has been… (More)

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