Performance comparison of MCML and PFSCL gates in 0.18 μm CMOS technology

@article{Gupta2011PerformanceCO,
  title={Performance comparison of MCML and PFSCL gates in 0.18 μm CMOS technology},
  author={Kirti Gupta and Ranjana Sridhar and Jaya Chaudhary and Neeta Pandey and Maneesha Gupta},
  journal={2011 2nd International Conference on Computer and Communication Technology (ICCCT-2011)},
  year={2011},
  pages={230-233}
}
In this paper, the performance of two popular source coupled logic styles, namely, MOS Current Mode Logic (MCML) and Positive Feedback Source Coupled Logic (PFSCL) is investigated. A number of SPICE simulation runs have been carried out using 0.18 μm CMOS technology parameters. The PFSCL circuit show better results than the MCML circuit in terms of propagation delay and area. The effect of process variations through Monte Carlo simulations however shows lower variations in MCML circuits style. 

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