Performance and structures of scaled-down bipolar devices merged with CMOSFETs

@article{Higuchi1984PerformanceAS,
  title={Performance and structures of scaled-down bipolar devices merged with CMOSFETs},
  author={H. Higuchi and G. Kitsukawa and T. Ikeda and Y. Nishio and N. Sasaki and K. Ogiue},
  journal={1984 International Electron Devices Meeting},
  year={1984},
  pages={694-697}
}
Fabricating BiCMOS test samples, performance and structures of 2 µm and scaled BiCMOS are evaluated. The developed BiCMOS processes realize almost the same device characteristics of bipolar and CMOS LSIs fabricated with the same lithographic technology. The intrinsic delays of BiCMOS and CMOS 2-NAND circuits are 0.5 ns and 0.4 ns respectively. The delay times are comparable with the bipolar ECL circuits. The BiCMOS technology makes it possible to fabricate high-speed, low-power dissipation… Expand

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