Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor

  title={Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor},
  author={Scott Hanson and Bo Zhai and Mingoo Seok and Brandon N. Cline and Keqin Zhou and Manu Singhal and Michael Minuth and Javin Olson and Leyla Nazhandali and Todd Austin and Dennis Sylvester and David Blaauw},
  journal={2007 IEEE Symposium on VLSI Circuits},
A robust, energy efficient subthreshold (sub-V<sub>th</sub>) processor has been designed and tested in a 0.13 mum technology. The processor consumes 11 nW at V<sub>dd</sub> = 160 mV and 3.5 pJ/inst at V<sub>dd</sub> = 350 mV. Variability and performance optimization techniques are investigated for sub-V<sub>th</sub> circuits. 
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