Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

@article{Shin2010PerformanceAA,
  title={Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node},
  author={Changhwan Shin and Min Hee Cho and Yasumasa Tsukamoto and Bich-Yen Nguyen and Carlos Mazurex0301 and Borivoje Nikolicx0301 and Tsu-Jae King Liu},
  journal={IEEE Transactions on Electron Devices},
  year={2010},
  volume={57},
  pages={1301-1309}
}
The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are… CONTINUE READING
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