Performance Optimization Using Variable-Latency Design Style

@article{Su2011PerformanceOU,
  title={Performance Optimization Using Variable-Latency Design Style},
  author={Yu-Shih Su and Da-Chung Wang and Shih-Chieh Chang and Malgorzata Marek-Sadowska},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2011},
  volume={19},
  pages={1874-1883}
}
In many designs, the worst-case delay of a critical path may be activated infrequently. Traditional optimization approaches assume the worst-case conditions, which could lead to an inefficient resource usage. It is possible to improve the throughput of such designs by introducing variable latency. One existing realization of the variable-latency design style is based on telescopic units. The design of the hold logic in telescopic units influences the circuit's throughput. In this paper, we show… CONTINUE READING
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