Performance Benefits of Monolithically Stacked 3-D FPGA
@article{Lin2007PerformanceBO, title={Performance Benefits of Monolithically Stacked 3-D FPGA}, author={Mingjie Lin and Abbas El Gamal and Yi-Chang Lu and S. Simon Wong}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, year={2007}, volume={26}, pages={216-229} }
The performance benefits of a monolithically stacked three-dimensional (3-D) field-programmable gate array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing logic blocks (LBs) and interconnects, are investigated. A Virtex-II-style two-dimensional (2-D) FPGA fabric is used as a baseline architecture to quantify the relative improvements in logic density, delay, and power consumption achieved by such a 3-D FPGA. It is assumed that only the…
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From the Publisher:
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