Performance Analysis of Full Adder Circuit using Double Gate MOSFET


This paper presents a design of a one bit full adder cell based on stack effect using Double Gate MOSFET. This design has been compared with existing one-bit full adder which is designed using power gating technique. In this paper, the proposed circuit has been analyzed for parameters likepower consumption and power delay product. The simulations of the… (More)


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@inproceedings{Chopra2015PerformanceAO, title={Performance Analysis of Full Adder Circuit using Double Gate MOSFET}, author={Mohit P. Chopra and Navneet Kaur Gill and Harjeet Singh and Ravindra Singh Kushwah and Shyam Akashe and Amara Amara and Chetan D. Parikh and Massimo Alioto and Gaetano Palumbo and Anuj Kumar Shrivastava and Jin-Fa Lin and Yin-Tsung Hwang and Ming-Hwa Sheu and Shipra Mishra and Shelendra Singh Tomar}, year={2015} }